The present invention relates to a production of a semiconductor device. More particularly, it relates to a method of forming an interconnecting structure between a conductor line and a doped region of a silicon substrate (or another lower conductor line) through a contact hole formed in an insulating layer.
The density or integration of semiconductor devices such as ICs has been increased, and accordingly, an area of a semiconductor substrate in contact with an electrode has become smaller than in the prior art and/or a conductor multilayer structure has been adopted. In the former case, a window (i.e., contact hole) is formed in an insulating layer formed on the semiconductor substrate, and in the latter case, a contact hole is formed in an insulating layer formed between the upper and lower conductor lines. In both cases the contact hole is made smaller, therefore the ratio of the opening width to the hole depth becomes smaller, making the side of the hole steeper. When a conductor layer (e.g., a commonly used aluminum layer) is deposited on the insulating layer so that it will connect with the semiconductor substrate or the lower conductor line, step coverage defects, such as breakdown or a very thin portion formation at the edge of a contact hole and the generation of deep crack inside the contact hole occur.
To prevent the occurrence of these step coverage defects, the contact hole only is filled with silicon (in this case, the silicon is doped to provide it with a certain conductivity) to obtain a flat surface at the insulating layer and the filled silicon. Thereafter a conductor layer of, e.g., aluminum, is deposited on the flat surface in such a manner that no step coverage defects occur. The filling of a contact hole only with silicon is carried out by (1) a method of selectively epitaxial growing silicon or (2) a method comprising the steps of vapor depositing polycrystalline silicon on the whole surface and selectively etching the portion on the insulating layer except within the contact hole. The first method is disclosed in, for example, N. Endo et al: "CMOS Technology Using Isolation Technique", IEEE Int. Electron Devices Meeting, Tech. Dig., pp. 31-34 (1983) and H. J. Voss, H. Kurten: "Device Isolation Technology by Selective Low-Pressure Silicon Epitaxy", IEEE Int. Electron Devices Meeting, Tech. Dig., pp. 35-38 (1982). In the second method, the polycrystalline silicon is formed by a conventional chemical vapor deposition (CVD) method and is used as a material for silicon gates of MOSFETs, conductive lines, etc. Such single crystalline or polycrystalline silicon is doped to a resistivity of 4-6.times.10.sup.-4 ohm.cm. The contact hole size, i.e., a crosssectional area of the filled silicon, is made smaller, so that a resistance of the filled silicon within the contact hole is increased. This increase in the resistance causes an increase in the delay time of the signal transmission.
The use of a refractory metal instead of silicon can reduce the delay time of the signals, since the refractory metal, such as tungsten (W), molybdenum (Mo) and the like has a lower resistivity than that of doped silicon by more than one order. A planar process in which a contact hole is filled with tungsten by a CVD method is disclosed in, e.g., T. Moriya et al: "A Planar Metallization Process--its Application to Tri-Level Aluminum Interconnection", IEEE Int. Electron Devices Meeting Tech. Dig., pp. 550-553 (1983). In this case, however, disadvantages occur in that the deposition rate of the tungsten is low (about 4.7 nm/min in the method as described later) so that the deposition time for filling the contact hole is long and that tungsten may be deposited on an insulating layer of SiO.sub.2. Moreover, the present inventors found that it is difficult to obtain good reproducibility when forming a contact hole in an insulating layer having a thickness of about 1.0 .mu.m, and selectively filling the contact hole with tungsten by a CVD method.